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4-BIT SINGLE CHIP MICROCOMPUTERS
GMS34XXXT SERIES
USERS MANUAL
* GMS34004T * GMS34112T * GMS34140T
Revision 1.1 Published by MCU Application Team in HYNIX Semiconductor Inc. All Right Reserved. Editor's E-Mail : rhja@hynix.com
Additional information of this manual may be served by HYNIX Semiconductor Inc.Offices in Korea or Distributors and Representative listed at address directory. HYNIX Semiconductor Inc.reserves the right to make changes to any Information here at any time without notice. The information, diagrams, and other data in this manual are correct and reliable; however, HYNIX Semiconductor Inc.is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
Table of Contents
Table of Contents
Chapter 1 Introduction ............................................................................................1-1
Outline of Characteristics .................................................................1-1 Characteristics ..................................................................................1-1 Block Diagram ..................................................................................1-2 Pin Assignment and Terminal ..........................................................1-3 Pin Dimension ..................................................................................1-4 Pin Description and Circuit .................................................................1-7 I/O circuit types and options .............................................................1-8 Electrical Characteristics ................................................................1-10 Chapter 2 Architecture ...........................................................................................2-1
Block Description .............................................................................2-1 Program Memory (ROM) ..................................................................2-1 EPROM Address Register ................................................................2-2 Data Memory (RAM) ........................................................................2-3 X-Register (X) ...................................................................................2-3 Y-Register (Y) ...................................................................................2-4 Accumulator (Acc) ............................................................................2-4 Arithmetic and Logic Unit (ALU) .......................................................2-4 State Counter (SC) ...........................................................................2-5 Clock Generator ...............................................................................2-6 Pulse Generator ...............................................................................2-7 Initial Reset Circuit ............................................................................2-8 Watch Dog Timer (WDT) .................................................................2-8 Stop Function ....................................................................................2-9 Port Operation ..................................................................................2-9
Chapter 3 Instruction ........................................................................................3-1
Table of Contents
Chapter 4 EPROM .................................................................................................4-1 GMS34004TK/34112TK/34140TK .........................................................4-1 Mode Define .....................................................................................4-1 Port Define .......................................................................................4-2 Programming Data ...........................................................................4-2 Write/Read Data Conversion ............................................................4-3 Checksum .........................................................................................4-3 Programming Control ........................................................................4-3 Programming DC Specification .........................................................4-3 EPROM read mode(1/2) ...................................................................4-4 EPROM read mode (2/2) ..................................................................4-4 EPROM write mode (1/2) ..................................................................4-5 EPROM write mode (2/2) ..................................................................4-5 Lock bit write mode (1/2) ..................................................................4-6 Lock bit write mode (2/2) ..................................................................4-6 Lock bit read mode (1/2) ..................................................................4-7 Lock bit read mode (2/2) ..................................................................4-7 GMS34004T/112T/140T (Pin assignment & Package) .....................4-8 EPROM (KHz) mode .........................................................................4-9 EPROM write only mode ..................................................................4-9 GMS34004TK/34112TK/34140TK .............................................................4-10
Mode Define .....................................................................................4-10 Port Define ........................................................................................4-11 Programming Data ...........................................................................4-11 Write/Read Data Conversion ............................................................4-12 Checksum ........................................................................................4-12 Programming Control ......................................................................4-12 Programming DC Specification ........................................................4-12 EPROM read mode(1/2) ...................................................................4-13 EPROM read mode (2/2) ...................................................................4-13 EPROM write mode (1/4) ..................................................................4-14 EPROM write mode (2/4) ..................................................................4-14 EPROM write mode (3/4) ..................................................................4-15 EPROM write mode (4/4) ..................................................................4-15 Lock bit write mode (1/3) ..................................................................4-16 Lock bit write mode (2/3) ..................................................................4-16 Lock bit write mode (3/3) ..................................................................4-16 Lock bit read mode (1/2) ..................................................................4-18 Lock bit read mode (2/2) ..................................................................4-18
INTRODUCTION ARCHITECTURE INSTRUCTION EPROM
1 2 3 4
Chapter 1. Introduction
CHAPTER 1. Introduction
OUTLINE OF CHARACTERISTICS
The GMS340 series are remote control transmitter which uses CMOS technology, and the EPROM version of GMS34XXX series. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS340 series are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipments, Toys, Games etc. Characteristics * * * * * * * * * * * * * Program memory : 512bytes for GMS34004T 1,024 bytes for GMS34112T/140T Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting 1 bit output port for a large current (REMOUT signal) Operating frequency :300KHz~500KHz at KHz version 2.4MHz~4MHz at MHz version 300KHz~4.2MHz at WIDE version Instruction cycle : f OSC/6 at KHz and WIDE version f OSC/48 at MHz version CMOS process (3.0V or 5.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input Built in capacitor for ceramic oscillation circuit at KHz version Built in a watch dog timer (WDT) Low operating voltage : 2.2~4.5V (at KHz and MHz version) Normal operating voltage: 4.0~5.0V (at WIDE version)
Series
Program memory Data memory I/O ports Input ports Output ports Package
KHz version MHz version WIDE version
GMS34004T
512 32 4 4 6 D0 ~ D5 16DIP GMS34004TK GMS34004TM GMS34004TW
GMS34112T
1,024 c 4 c c c 20DIP/SOP/SSOP GMS34112TK GMS34112TM GMS34112TW
GMS34140T
c c c c 10 D0 ~ D9 24DIP/SOP GMS34140TK GMS34140TM GMS34140TW
Table 1-1 GMS34XXXT series members
1- 1
Chapter 1. Introduction Block Diagram
RESET/Vpp 1
VDD 24
GND 2
Reset ROM 64word 16page 8bit 4 8 MUX Instruction Decoder 4 4 MUX 4 Control Signal X-Reg 2 RAM 16word x 2page x 4bit 16 RAM Word Selector Y-Reg 4 ACC 4 OSC R-Latch 10 D-Latch 4 Pulse Generator 4 23 22 7 8 9 10 4 3 4 4 5 6 11 12 13 14 10 15 16 17 18 19 20 21 REMOUT ST ALU 4 10 Program counter 10 4 Watchdog timer
Stack
8
OSC1 OSC2
K0 ~ K3
R0 ~ R3
D0 ~ D9
Fig 1-1 Block Diagram (In case of GMS34140T)
1- 2
Chapter 1. Introduction Pin Assignment and terminals Pin Assignment
RESET/Vpp GND K0 K1 K2 K3 D0 D1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD OSC1 OSC2 REMOUT D5 D4 D3 D2
K0 K1 K2 K3 D0 D1 D2 D3 D4 D5
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
R3 R2 R1 R0 GND RESET/Vpp VDD OSC1 OSC2 REMOUT
Fig 1-2 GMS34004T Pin Assignment (16PDIP)
Fig 1-3 GMS34112T Pin Assignment (20DIP/SOP)
GND R0 R1 R2 R3 K0 K1 K2 K3 D0
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
RESET/Vpp VDD OSC1 OSC2 REMOUT D5 D4 D3 D2 D1
RESET/Vpp GND R0 R1 R2 R3 K0 K1 K2 K3 D0 D8
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD OSC1 OSC2 REMOUT D7 D6 D5 D4 D3 D2 D1 D9
Fig 1-4 GMS34112T Pin Assignment (20SSOP only)
Fig 1-5 GMS34140T Pin Assignment (24DIP/SOP)
1- 3
Chapter 1. Introduction
Pin Dimension
16 15 14 13 12 11 10 9
0.170MAX
0.135MAX 0.125MIN
1
2
3
4
5
6
7
8
0.300BSC 0.260MAX 0.240MIN 0.140MAX 0.120MIN
0.785MAX 0.745MIN
0.015MIN
0.065MAX 0.050MIN 0.100BSC 0.022MAX 0.015MIN 0.040MAX 0.020MIN
ae
c 0.008MIN
0.014MAX
ae c
0~15C
Outline (Unit:Inch)
Fig 1-6 16PDIP Pin Dimension
20 19 18 17 16 15 14 13 12 11
1
2
3
4
5
6
7
8
9
10
0.3TYP 0.270MAX 0.250MIN
0.984MAX 0.968MIN
0.170MAX
0.015MIN
0.1TYP 0.065MAX 0.055MIN 0.022MAX 0.015MIN
0.135MAX 0.125MIN
ae
c 0.008MIN
0.012MAX
ae
c
0~15C
Outline (Unit : Inch)
Fig 1-7 20PDIP Pin Dimension
1- 4
Chapter 1. Introduction
20
19
1 8 17
16
15
14
13
12
11
1 0.104MAX 0.093MIN
2
3
4
5
6
7
8
9
10 0.419MAX 0.398MIN 0.299MAX 0.292MIN
0.5118MAX 0.4961MIN
0.0118MAX 0.004MIN
0.020MAX 0.014MIN
0.05TYP
0.0125MAX 0.0091MIN
Outline (Unit : Inch)
Fig 1-8 20SOP Pin Dimension
ae c
ae
c0.016MIN
0.042MAX
20
19
1 8 17
16
15
14
13
12
11
1 0.066MAX 0.057MIN
2
3
4
5
6
7
8
9
10
0.244MAX 0.234MIN 0.157MAX 0.150MIN 0.010MAX 0.007MIN
0.344MAX 0.337MIN
ae c
0-8 e
e
0.010MAX 0.004MIN 0.012MAX 0.008MIN 0.025BSC
ae
c 0.032MAX
0.022MIN
Outline (Unit : Inch)
Fig 1-9 20SSOP Pin Dimension
1- 5
Chapter 1. Introduction
24
23
22
21
20
19
18
17
16
15
14
13
0.170MAX
1
2
3
4
5
6
7
8
9
10
11
12
0.3TYP 0.270MAX 0.250MIN
1.255MAX 1.245MIN
0.015MIN
0.1TYP 0.065MAX 0.055MIN 0.022MAX 0.015MIN
0.135MAX 0.125MIN
ae
c 0.008MIN
0.012MAX
ae
c
0~15
Outline (Unit : Inch)
Fig 1-10 24Skinny DIP Pin Dimension
24
23
22
21
20
19
18
17
16
15
14
13
1 0.104MAX 0.093MIN
2
3
4
5
6
7
8
9
10
11
12
0.419MAX 0.398MIN 0.299MAX 0.292MIN
0.616MAX 0.595MIN
ae c
0.05TYP 0.020MAX 0.018MAX 0.004MIN 0.014MIN
ae
0.0125MAX 0.0091MIN
c0.016MIN
0.042MAX
Outline (Unit : Inch)
Fig 1-11 24SOP Pin Dimension
1- 6
Chapter 1. Introduction Pin Description and Circuit Pin Description
Pin
VDD
I/O
-
Function
Connected to 2.2~4.5V power supply at KHz and MHz version or 4.0 ~ 5.5V power supply at WIDE version. Connected to 0V power supply. Used to input a manual reset. When the pin goes "L", the D-output ports and REMOUT-output port are initialized to "L", and ROM address is set to address 0 on page 0. For programming, this pin receives 12.5V programming voltage. 4-bit input port. STOP mode is released by "L" input of each pin. The output is the structure of N-channel-open-drain. 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. STOP mode is released by "L" input of each pin. High current output port. The output is in the form of C-MOS. The state of large current on is "H". Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at KHz version. A feedback resistor is connected between this pin and OSC2. Connect a resonator between this pin and OSC1.
GND
-
RESET
Input
K0~K3 D0~D9
Input Output
R0~R3
I/O
REMOUT
Output
OSC1
Input
OSC2
Output
1- 7
Chapter 1. Introduction
I/O circuit types and options
Pin I/O I/O circuit
ae Reset/Vpp I ae c c Hysteresis Input Type. Built in pull-up-resistor, Typical 800U
Note
c R0~R3 I/O
pull-up
ae c
ae
CMOS output. "H" output at reset. Built in MOS Tr for pull-up about 120U.
ae K0~K3 I
pull-up
ae c
Built in MOS Tr for pull-up About 120U.
D0~D9
O
c
Open drain output. "L" output at reset.
ae REMOUT O c
CMOS output. "L" output at reset. High current output source.
1- 8
Chapter 1. Introduction
Pin
I/O
STOP
I/O circuit
Note
Built in feedback-resistor about 1U
OSC2
O
OSC1
ae ae c
c
Rd
OSC2
Built in damping-resistor Rd = 4U [No resistor in MHz operation] Built in resonance Capacitor at KHz version C1=C2 = 100pF 3/415% [C1,C2 are not available for MHz and WIDE version]
OSC1
I
e C1 e Rf C2
Frequency
320KHz 500KHz 3.43MHz 3.52MHz 3.64MHz 3.84MHz 4.00MHz
Resonator Maker
CQ CQ CQ TDK CQ TDK CQ TDK CQ
Part Name
ZTB320D ZTB500E ZTA3.43MG FCR3.52M5 ZTA3.64MG FCR3.64M5 ZTA3.84MG FCR3.84M5 ZTA4.00MG
Load Capacitor
C1=C2=Open C1=C2=Open C1=C2=30pF C1=C2=33pF C1=C2=30pF C1=C2=33pF C1=C2=30pF C1=C2=33pF C1=C2=30pF
CQ recommend 430KHz~500KHz resonator
1- 9
Chapter 1. Introduction Electrical Characteristics Absolute maximum ratings (Ta = 25E)
Parameter
Supply Voltage Programming Voltage Power dissipation Storage temperature range Input voltage Output voltage
Symbol
VDD VPP PD Tstg VIN VOUT
Max. rating
-0.3 ~ 7.0 -0.3 ~ 13.5 700 * -55 ~ 125 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3
Unit
V V mW E V V
* Thermal derating above 25E : 6mW per degree E rise in temperature.
Recommended operation condition
Parameter Symbol Condition
300 ~ 500KHz Supply Voltage VDD 2.4 ~ 4MHz 300KHz ~ 4.2MHz Operating temperature Topr -
Rating
2.2 ~ 4.5 2.2 ~ 4.5 4.0 ~ 5.5 -20 ~ +70
Unit
V
E
1 - 10
Chapter 1. Introduction
Electrical characteristics for low voltage products (Ta=25E, VDD=3V)
Limits Parameter Symbol Min.
Input H current RESET input L current K, R input L current IIH IIL2 IIL1 VIH1 VIL1 VIH2 VIL2 VOL2 VOL1 VOH1 VOL3 VOH3 IOL ISTOP IDD1 * IDD2 * fOSC fOSC -2 -9 2.1 2.25 2.1 2.1 300 2.4
Unit Typ.
-7.5 -25 0.15 0.15 2.5 0.4 2.5 0.3 0.5 -
Condition
Max.
1 -16 -50 0.9 0.75 0.4 0.4 0.9 1 1 4.0 4.0 500 4 uA uA uA V V V V V V V V V uA uA mA mA KHz MHz VI=VDD VI=GND VI=GND, Output off, Pull-Up resistor provided. V IOL=1mA IOL=100uA IOH=-8mA IOL=70uA IOH=70uA V0UT=VDD, Output off At STOP mode fOSC=455KHz fOSC=4MHz KHz version MHz version
K, R input H voltage K, R input L voltage RESET input H voltage RESET input L voltage D. R output L voltage REMOUT output L voltage REMOUT output H voltage OSC2 output L voltage OSC2 output H voltage D, R output leakage current Current on STOP mode Operating supply current 1 Operating supply current 2 System clock frequency fOSC/6 fOSC/48
* IDD1, IDD2, is measured at RESET mode.
1 - 11
Chapter 1. Introduction
Electrical characteristics (Ta=25E, VDD=5V)
Limits Parameter Symb ol
IIH IIL2 IIL1 VIH1 VIL1 VIH2 VIL2 VOL2 VOL1 VOH1 VOL3 VOH3 IOL ISTOP IDD fOSC
Unit Min.
-2 -9 0.7*VDD 0.75*VDD VDD-1.0 VDD-1.0 0.3
Condition
Typ.
-
Max.
5 -20 -150 0.3*VDD 0.25*VDD 0.4 0.4 0.9 5 10 10 4.2 uA uA uA V V V V V V V V V uA uA mA MHz VI=VDD VI=GND VI=GND, Output off, Pull-Up resistor provided. V IOL=2mA IOL=100uA IOH=-8mA IOL=70uA IOH=-70uA V0UT=VDD, Output off At STOP mode At RESET mode WIDE version
Input H current RESET input L current K, R input L current
K, R input H voltage K, R input L voltage RESET input H voltage RESET input L voltage D. R output L voltage REMOUT output L voltage REMOUT output H voltage OSC2 output L voltage OSC2 output H voltage D, R output leakage current Current on STOP mode Operating supply current System clock frequency fOSC/6
1 - 12
INTRODUCTION ARCHITECTURE INSTRUCTION EPROM
1 2 3 4
Chapter 2. Architecture
CHAPTER 2. Architecture
BLOCK DESCRIPTION
Program Memory (EPROM) The GMS34XXXT series can incorporate maximum 1,024 words (64 words16 pages8bits) for program memory. Program counter PC (A0~A5) and page address register (A6~A9) are used to address the whole area of program memory having an instruction (8bits) to be next executed. The program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. The program memory is composed as shown below.
Program capacity (pages)
01 8
23 45 67
Page 0
Page 1
Page 2
Page 15
63
0 A0~A5 Program counter (PC) 6 Stack
1
2
15 A6~A9
Page address register (PA) 4 register (Level "1") (Level "2")
4
Page buffer (PB)
(SR)
(PSR)
(Level "3")
Fig 2-1 Configuration of Program Memory
2- 1
Chapter 2. Architecture EPROM Address Register The following registers are used to address the EPROM. * Page address register (PA) : Holds EPROM's page number (0~Fh) to be addressed. * Page buffer register (PB) : Value of PB is loaded by an LPBI command when newly addressing a page. Then it is shifted into the PA when rightly executing a branch instruction (BR) and a subroutine call (CAL). * Program counter (PC) : Available for addressing word on each page. * Stack register (SR) : Stores returned-word address in the subroutine call mode. (1) Page address register and page buffer register : Address one of pages #0 to #15 in the EPROM by the 4-bit binary counter. Unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. To change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL, because instruction code is of eight bits so that page and word can not be specified at the same time. In case a return instruction (RTN) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. (2) Program counter : This 6-bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed. For easier programming, at turning on the power, the program counter is reset to the zero location. The PA is also set to "0". Then the program counter specifies the next EPROM address in random sequence. When BR, CAL or RTN instructions are decoded, the switches on each step are turned off not to update the address. Then, for BR or CAL, address data are taken in from the instruction operands (a0 to a5), or for RTN, and address is fetched from stack register No. 1. (3) Stack register : This stack register provides two stages each for the program counter (6 bits) and the page address register (4bits) so that subroutine nesting can be made on two levels.
2- 2
Chapter 2. Architecture Data memory (RAM) Up to 32 nibbles (16 words 2pages 4bits) is incorporated for storing data. The whole data memory area is indirectly specified by a data pointer (X,Y). Page number is specified by zero bit of X register, and words in the page by 4 bits in Y-register. Data memory is composed in 16 nibbles/page. Figure 2-2 shows the configuration.
D0
D9 R0
R3 REMOUT
Data memory page (0~1)
Output port
0
1
2
3
Page 0
Page 1
15
4
A0~A3
0
1
Y-register (Y)
X-register (X)
4
2
Fig 2-2 Composition of Data Memory
X-register (X) X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only used for selecting of D8~D9 with value of Y-register
X1=0
Y=0 Y=1 D0 D1
X1=1
D8 D9
Table 2-1 Mapping table between X and Y register
2- 3
Chapter 2. Architecture Y-register (Y) Y-register has 4 bits. It operates as a data pointer or a general-purpose register. Y-register specifies and address (a0~a3) in a page of data memory, as well as it is used to specify an output port. Further it is used to specify a mode of carrier signal outputted from the REMOUT port. It can also be treated as a generalpurpose register on a program. Accumulator (ACC) The 4-bit register for holding data and calculation results. Arithmetic and Logic Unit (ALU) In this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) (1) Operation circuit (ALU) : The adder/comparator serves fundamentally for full addition and data comparison. It executes subtraction by making a complement by processing an inversed output of ACC (ACC+1) (2) Status logic : This is to bring an ST, or flag to control the flow of a program. It occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal.
2- 4
Chapter 2. Architecture State Counter (SC) A fundamental machine cycle timing chart is shown below. Every instruction is one byte length. Its execution time is the same. Execution of one instruction takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total). Virtually these two cycles proceed simultaneously, and thus it is apparently completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN instructions is normal execution time since they change an addressing sequentially. Therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle.
T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 Fetch cycle N Execute cycle N-1 Phase Execute cycle N Fetch cycle N-1
Phase
Phase Machine Cycle Machine Cycle
Fig. 2-3 Fundamental timing chart
2- 5
Chapter 2. Architecture
Clock Generator The GMS34XXXT series has an internal clock oscillator. The oscillator circuit is designed to operate with an external ceramic resonator. Internal capacitors are available at KHz version. Oscillator circuit is able to organize by connecting ceramic resonator to outside. * It is necessary to connect capacitor to outside in order to change ceramic resonator, you must refer to a manufacturers resonator matching guide.
OSC1
OSC2
OSC1 23
OSC2 22
23 C1
22 C2

Version
KHz
Operating Frequency
300KHz ~ 500KHz Internal capacitor No Internal capacitor
Oscillation Circuit
Circuit 2 Circuit 1 Circuit 1 Circuit 1
MHz WIDE
2.4MHz ~ 4MHz 300KHz ~ 4.2MHz
No Internal capacitor No Internal capacitor
2- 6
Chapter 2. Architecture
Pulse generator The following frequency and duty ratio are selected for carrier signal outputted from the REMOUT port depending on a PMR (Pulse Mode Register) value set in a program.
T
T1
PMR
0 1 2 3 4 5 6 7
REMOUT signal
T=1/fPUL = 12/fOSC [96/fOSC], T=1/fPUL = 12/fOSC [96/fOSC], T=1/fPUL = 8/fOSC [64/fOSC], T=1/fPUL = 8/fOSC [64/fOSC], T=1/fPUL = 11/fOSC [88/fOSC], No Pulse (same to D0~D9) T=1/fPUL = 12/fOSC [96/fOSC], No pulse (same to D0 ~ D9) T1/T = 1/4 T1/T = 1/2 T1/T = 1/3 T1/T = 1/2 T1/T = 1/4 T1/T = 4/11
* Default value is "0" * [ ] means the value of "T", when Instruction cycle is fOSC/48 in MHz version
Table 2-2 PMR selection table
2- 7
Chapter 2. Architecture Initial Reset Circuit RESET pin must be down to "L" more than 4 machine cycle by outside capacitor or other for power on reset. The mean of 1 machine cycle is 6/fOSC or 48/fOSC, however, operating voltage must be in recommended operating conditions, and clock oscillating stability. * It is required to adjust C value depending on rising time of power supply. (Example shows the case of rising time shorter than 10ms.)
1 RESET 0.1uF
Watch Dog Timer (WDT) Watch dog timer is organized binary of 14 steps. The signal of fOSC/6 cycle comes in the first step of WDT after WDT reset. If this counter was overflowed, reset signal automatically come out so that internal circuit is initialized. The overflow time is 62 13/fOSC (108.026ms at fOSC=455KHz.) 86213/fOSC (108.026ms at fOSC = 3.64MHz) Normally, the binary counter must be reset before the overflow by using reset instruction (WDTR) or / and REMOUT port HIGH(Y-reg=8, So instruction execution). * It is constantly reset in STOP mode. When STOP is released, counting is restarted. (Refer to 2-9 STOP function>)
fOSC/6 or fOSC/48
Binary counter (14 steps) RESET (edge-trigger)
CPU reset
Reset by instruction REMOUT output
2- 8
Chapter 2. Architecture
STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, D8~D9 output and REMOUT output are "L". 3. Part other than WDT, D8~D9 output and REMOUT output have a value before come into stop mode. Stop mode is released when one of K or R input is going to "L". 1. State of D0~D7 output and REMOUT output is return to state of before stop mode is achieved. 2. After 1,0248 enable clocks for stable oscillating, First instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction.
Port Operation
Value of X-reg 0 or 1 Value of X-reg 0~7 S0 : D(Y) c 1, Operation R0 : D(Y) c 0
0 or 1
8
REMOUT port repeats "H" and "L" in pulse frequency. (When PMR = 5, it is fixed at "H") S0 : REMOUT(PMR) c 1 R0 : REMOUT(PMR) c 0 S0 : D0 ~ D9 c 1 (High-Z) R0 : D0 ~ D9 c 0 S0 : R(Y-Ah) c 1 R0 : R(Y-Ah) c 0 S0 : R0 ~ R3 c 1 R0 : R0 ~ R3 c 0 S0 : D0 ~ D9 c 1, R0 ~ R3 c 1 R0 : D0 ~ D9 c 0, R0 ~ R3 c 0 S0 : D(8) c 1 R0 : D(8) c 0 S0 : D(9) c 1 R0 : D(9) c 0
0 or 1 0 or 1 0 or 1 0 or 1 2 or 3 2 or 3
9 A~D E F 0 1
2- 9
INTRODUCTION ARCHITECTURE INSTRUCTION EPROM
1 2 3 4
Chapter 3. Instruction
CHAPTER 3. Instruction
Instruction Table The GMS34XXXT series provides the following 43 basic instructions.
Category
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Arithmetic ROM Address RAM Bit Manipulation Immediate RAM to Register Register to Register
Mnemonic
LAY LYA LAZ LMA LMAIY LYM LAM XMA LYI i LMIIY i LXI n SEM n REM n TM n BR a CAL a RTN LPBI i AM SM IM DM IA IY DA A c Y Y c A A c 0 M(X,Y) c A
Function
ST*1
S S S S S S S S S S S S S E S S S S C B C B S C B
M(X,Y) c A, Y c Y+1 Y c M(X,Y) A c M(X,Y) A e M(X,Y) Y c i M(X,Y) c i, Y c Y+1 X c n M(n) c 1 M(n) c 0 TEST M(n) = 1 if ST = 1 then Branch if ST = 1 then Subroutine call Return from Subroutine PB c i A c A + M(X,Y) A c M(X,Y) - A A c M(X,Y) + 1 A c M(X,Y) - 1 A c A + 1 Y c Y + 1 A c A - 1
3- 1
Chapter 3. Instruction
Category
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Control 42 43 Input / Output Comparison Arithmetic
Mnemonic
DY EORM NEGA ALEM ALEI i MNEZ YNEA YNEI i KNEZ RNEZ LAK LAR SO RO WDTR STOP LPY NOP Y c Y - 1
Function
ST*1
B S Z E E N N N N N S S S S S S S S
A c A + M (X,Y) A c A + 1 TEST A A M(X,Y) TEST A A i TEST M(X,Y) A 0 TEST Y A A TEST Y A i TEST K A 0 TEST R A 0 A c K A c R Output(Y) c 1*2 Output(Y) c 0*2 Watch Dog Timer Reset Stop operation PMR c Y No operation
Note) i = 0~f, n = 0~3, a = 6bit PC Address *1 Column ST indicates conditions for changing status. Symbols have the following meanings S : On executing an instruction, status is unconditionally set. C : Status is only set when carry or borrow has occurred in operation. B : Status is only set when borrow has not occurred in operation. E : Status is only set when equality is found in comparison. N : Status is only set when equality is not found in comparison. Z : Status is only set when the result is zero. *2 Operation is settled by a value of Y-register.
3- 2
INTRODUCTION ARCHITECTURE INSTRUCTION EPROM
1 2 3 4
Chapter 4. EPROM
CHAPTER 4. EPROM
GMS34004TK / 34112TK / 34140TK
Mode define
Item
User mode EPROM read mode 1Byte PGM Write EPROM Program mode 2Byte PGM Write Program verify Lock bit Program mode Lock bit Write Lock bit Read
Device operation
Exact User pgm Address in, Data out Address in, Data in Address in, Data in Address in, Data out Lock bit write(set D5 to 1) Lock bit out RESETB =12.5V
Mode setting
RESETB = 0 ~ 3V RESETB =12.5V K3~0=0110 K3~0=0110 K3~0=0111 K3~0=0100 K3~0=0101 Vcc=6.0V, Lock bit is D5. (Default : unlock) Vcc=6.0V Vcc=3V Vcc=6.0V
RESETB =12.5V
4- 1
Chapter 4. EPROM
Port define
Port Name
VDD RESETB OSC1 K0 K1 K2 K3 D0 D1 D2 D3 D4 D5 GND
User Mode
3.0V Reset (0, 3.0V) Clock input K0(Input) K1(Input) K2(Input) K3(Input) D0(Output) D1(Output) D2(Output) D3(Output) D4(Output) D5(Output) 0V A0 A1 A2 A3 A4 6.0V
EPROM Mode
Vpp (0, 12.5V) Clock input
Read / Write Control Address / Data Control
A5 A6 A7 A8 A9
Da0 Da1 Da2 Da3 -
Da4 Da5 Da6 Da7 NMOS open drain I/O in EPROM mode
Lock bit output
* Undefined ports in this table are N.C (No Connection)
Programming data
Blank data Lock bit Device address (HEX)
FF FF FF Yes Yes Yes 0000 ~ 01FF 0000 ~ 03FF 0000 ~ 03FF
Device Name
GMS34004TK GMS34112TK GMS34140TK
ROM Size
512bytes 1,024bytes 1,024bytes
File address
0000 ~ 01FF 0000 ~ 03FF 0000 ~ 03FF
- If lock bit is set, the EPROM of the device can not be read, because output is always FF. - Input file : Intel Hexa format ( *.RHX )
4- 2
Chapter 4. EPROM
Write / Read data conversion
- You must change MSB ~ LSB e LSB ~ MSB. - Example File / buffer data Hex
2C E4 8D
Device (D3 ~ D0) Hex
Write 34 27 Read B1
Binary (MSB~LSB)
0010 1100 1110 0100 1000 1101
Binary (MSB~LSB)
0011 0100 0010 0111 1011 0001
Checksum
- It is calculated from the Buffer of the programmer. - Address range is the same as device address. - Calculate method is the same as normal EPROM devices (ex:27C128, 256 etc)
Programming control
- OSC1 & RESETB control OTP device, so you must count OSC1 clocks in every state. - K ports control the internal state of the OTP device(ex: Read, Write...). - D5~D0 ports are NMOS open drain I/O in EPROM mode. It must be pulled up by resistors (about 4.7~ 47K ohm). - The frequency rate of the OSC1 clock is 10KHz ~ 500KHz. You can hold OSC1 HIGH or LOW state when you need.
Programming DC specification
Item
VCC RESETB K-port D-port
Range
0 ~ 6.0V 3/4 0.25V 0 ~ 12.5V 3/4 0.5V 0 ~ 0.2VCC(Low) 0.8VCC ~ VCC (High)
4- 3
Chapter 4. EPROM
EPROM read mode (1/2)
For device verify or read. If you set Lock bit, output data is always FF.
14.5clocks c e OSC CK1 CK2 CK3 VCC RESETB K3 ~ K0 D4 ~ D0 6V 0V 0110
AH
2us at 500KHz o o
12.5V 0000
AL
1101
OH OL AH
0000
AL
1101
OH OL AH
0000
AL
1101
OH OL AH
0000
AL
1101
OH OL
Addr. 0
Addr. 1
Addr. 2
Addr. 3
1
2
3
AH : High Address (A9~5) Input Latch AL : Low Address (A4~0) Input Latch
OH : High Data (D7~4) Output OL : Low Data (D3~0) Output
* Note : 1. AH, AL, DH, DL Inputs released at 100~200nS after OSC rising edge and width is 1OSC cycle ( if OSC is 500KHz, width is 2uS ).
EPROM read mode (2/2)
START c Reset (Set EPROM read mode)
Address=First address e e
Set address
Read data
Address ++
Address > Last address
RESETB=0V VCC=0V
END
4- 4
Chapter 4. EPROM
EPROM write mode (1/2)
14.5clocks c e OSC CK1 CK2 CK3 VCC RESETB K3 ~ K0 D4 ~ D0 6V 0V 12.5V 0000
AH AL DH
2us at 500KHz o o
9.5V PGM Write ( 0110 )
1000
DL
1110
1101
OH OL
0000
AH AL DH
1000
DL
10times Repeat 12us X 10 = 120us 1 2 3 4
Verify
Next Write
AH : High bit Address Input Latch AL : Low bit Address Input Latch
DH : High bit Data Input Latch DL : Low bit Data Input Latch
OH : High bit Data Output OL : Low bit Data Output
* Note : 1. AH, AL, DH, DL Inputs are released at 100~200nS after OSC rising edge and width is 1OSC cycle ( if OSC is 500KHz, width is 2uS ).
EPROM write mode (2/2)
START c Reset (Set EPROM write mode) e EPROM write (Write one more time)
Address ++ Address=First address No e Set address & data Count=0 Address > Last address Yes RESETB=0V VCC=0V Pass
e EPROM write Repeat until near 100uS. When 500KHz OSC1, repeat 10 times (12uS*10=120uS)
EPROM read mode Verify all Fail Device fail
Device OK
Count ++ e Verify Fail No Count=25? Yes END Pass RESETB=0V VCC=0V
4- 5
Chapter 4. EPROM
Lock bit write mode (1/2)
14.5clocks
c e o o
2us at 500KHz
OSC CK1 CK2 CK3 VCC RESETB K3 ~ K0 6V 0V 12.5V Lock Write ( 0100 ) 0000 1110 10 times Repeat
12us X 10 = 120us
Lock bit write 1 2 3
Lock bit write mode (2/2)
START c Reset (Set Lock bit write mode) e Wait cycle Count=0 *1 Repeat until near 100uS. When 500KHz OSC1, repeat 10times (12uS * 10 = 120uS)
e
Write cycle *1
Count++ No
Count=10? Yes RESETB=0V VCC=0V
END
4- 6
Chapter 4. EPROM
Lock bit read mode (1/2)
14.5clocks
c e o o
2us at 500KHz
OSC1
VCC
6V 0V 12.5V Lock Read ( 0101 ) Lock bit output
1
2
Lock bit read mode (2/2)
START c Reset (Set Lock bit read mode) e Read Lock bit (D5)
RESETB=0V VCC=0V
END
4- 7
Chapter 4. EPROM
GMS34004T/112T/140T (Pin assignment & Package)
RESETB 1 GND 2 K0 3 K1 4 K2 5 K3 6 D0 7 D1 8
16 VDD 15 OSC1 14 13 12 D5 11 D4 10 D3 9 D2
16DIP (Standard TTL DIP Size) - Width 300mil - Pin to pin 100mil
K0 1 K1 2 K2 3 K3 4 D0 5 D1 6 D2 7 D3 8 D4 9 D5 10
20 19 18 17 16 GND 15 RESETB 14 VDD 13 OSC1 12 11 -
20DIP (Standard TTL DIP Size) - Width 300mil - Pin to pin 100mil
20SOP (Standard TTL SOP Size)
RESETB 1 GND 2 -3 -4 -5 -6 K0 7 K1 8 K2 9 K3 10 D0 11 - 12
24 VDD 23 OSC1 22 21 20 19 18 D5 17 D4 16 D3 15 D2 14 D1 13 -
24DIP (Skinny DIP Size) - Width 300mil - Pin to pin 100mil
24SOP (Standard SOP Size)
4- 8
Chapter 4. EPROM
EPROM(KHz) mode EPROM write only mode
14.5clocks c e OSC CK1 CK2 CK3 VCC RESETB K3 ~ K0 D4 ~ D0 6V 0V 12.5V PGM Write ( 0110 ) 0000
AH AL DH
2us at 500KHz o o
1000
DL
1110
0000
AH AL DH
1000
DL
1110
10times Repeat 12us X 10 = 120us 5times Repeat EPROM write
Next Write
4- 9
Chapter 4. EPROM
GMS34004TM / 34112TM / 34140TM
Mode define
Item
User mode EPROM read mode 1Byte PGM Write EPROM Program mode 2Byte PGM Write Program verify Lock bit Program mode Lock bit Write Lock bit Read
Device operation
Execute User pgm Address in, Data out Address in, Data in Address in, Data in Address in, Data out Lock bit write(set D5 to 1) Lock bit out RESETB =12.5V
Mode setting
RESETB = 0 ~ 3V RESETB =12.5V K3~0=0010 K3~0=0110 K3~0=0111 K3~0=0100 K3~0=0101 Vcc=6.0V, Lock bit is D5. (Default : unlock) Vcc=6.0V Vcc=3V Vcc=6.0V
RESETB =12.5V
4 - 10
Chapter 4. EPROM
Port define
Port Name
VDD RESETB OSC1 K0 K1 K2 K3 D0 D1 D2 D3 D4 D5 GND
User Mode
3.0V Reset (0, 3.0V) Clock input K0(Input) K1(Input) K2(Input) K3(Input) D0(Output) D1(Output) D2(Output) D3(Output) D4(Output) D5(Output) 0V A0 A1 A2 A3 A4 6.0V
EPROM Mode
Vpp (0, 12.5V) Clock input
Read / Write Control Address / Data Control
A5 A6 A7 A8 A9
Da0 Da1 Da2 Da3 -
Da4 Da5 Da6 Da7 NMOS open drain I/O in EPROM mode
Lock bit output
* Undefined ports in this table are N.C (No Connection)
Programming data
Blank data Lock bit Device address (HEX)
FF FF FF Yes Yes Yes 0000 ~ 01FF 0000 ~ 03FF 0000 ~ 03FF
Device Name
GMS34004TK GMS34112TK GMS34140TK
ROM Size
512bytes 1,024bytes 1,024bytes
File address
0000 ~ 01FF 0000 ~ 03FF 0000 ~ 03FF
- If lock bit is set, the EPROM of the device can not be read, because output is always FF. - Input file : Intel Hexa format ( *.RHX )
4 - 11
Chapter 4. EPROM
Write / Read data conversion
- You must change MSB ~ LSB e LSB ~ MSB. - Example File / buffer data Hex
2C E4 8D
Device (D3 ~ D0) Hex
Write 34 27 Read B1
Binary (MSB~LSB)
0010 1100 1110 0100 1000 1101
Binary (MSB~LSB)
0011 0100 0010 0111 1011 0001
Checksum
- It is calculated from the Buffer of the programmer. - Address range is the same as device address. - Calculate mathod is the same as normal EPROM devices (ex:27C128, 256 etc)
Programming control
- OSC1 & RESETB control OTP device, so you must count OSC1 clocks in every state. - K ports control the internal state of the OTP device(ex: Read, Write...). - D5~D0 ports are NMOS open drain I/O in EPROM mode. It must be pulled up by resistors (about 4.7~ 47K ohm). - The frequency rate of the OSC1 clock is 10KHz ~ 500KHz. You can hold OSC1 HIGH or LOW state when you need.
Programming DC specification
Item
VCC RESETB K-port D-port
Range
0 ~ 6.0V 3/4 0.25V 0 ~ 12.5V 3/4 0.5V 0 ~ 0.2VCC(Low) 0.8VCC ~ VCC (High)
4 - 12
Chapter 4. EPROM
EPROM read mode (1/2)
For device verify or read. If you set Lock bit, output data is all 'FF'
12Clock OSC1 8Clock
Address setting
Data read
1
2
3
Data Strobe point 5Clock
Data Strobe point 5Clock
VCC RESETB K3 ~ K0 D4 ~ D0 D5
6V 0V 12.5V ROM Dump Mode ( 0010 )
A9~A5 A4~A0 D7~D4 D3~D0
Port Operation
K Port Latch
High bit Address Latch
Low bit Address Latch
Sense AMP. Operation Repeat
High bit Instruction Output
Low bit Instruction Output
EPROM read mode (2/2)
START c Reset (Set EPROM read mode)
Address=First address e e
Set address
Read data
Address ++
Address > Last address
RESETB=0V VCC=0V END
4 - 13
Chapter 4. EPROM
EPROM write mode (1/4)
12Clock 8Clock
OSC1
1
2
2
VCC RESETB K3 ~ K0 D4 ~ D0
6V 0V PGM Write ( 0110 (1B))
A9~A5
12.5V 0000
A4~A0 D7~D4 D3~D0
1000
K Port Latch
High bit Address Latch
Low bit Address Latch
High bit Instruction Latch
Low bit Instruction Latch
First Address Input
First Data Input
EPROM write mode (2/4)
OSC1
3
3
4
VCC
6V
RESETB K3 ~ K0 D4 ~ D0
12.5V 1110 1110 1101
Verify EPROM write time
4 - 14
Chapter 4. EPROM
EPROM write mode (3/4)
OSC1
4
Data Strobe point 5Clock VCC 6V Verify RESETB K3 ~ K0 D4 ~ D0 12.5V 1101
D7~D4 D3~D0 A9~A5
2
Data Strobe point 5Clock
2
0000
A4~A0 D7~D4 D3~D0
1000
High bit Instruction Output
Low bit Instruction Output
High bit Address Latch
Low bit Address Latch
High bit Instruction Latch
Low bit Instruction Latch
Next Address Input
Next Data Input
EPROM write mode (4/4)
START c Reset (Set EPROM write mode) e EPROM write (Write one more time)
Address ++ Address=First address No e Set address & data Count=0 Address > Last address Yes RESETB=0V VCC=0V Pass
e EPROM write Repeat until near 100uS. When 4MHz OSC1, repeat 10 times (12uS*10=120uS)
EPROM read mode Verify all Fail Device fail
Device OK
Count ++ e Verify Fail No Count=25? Yes END Pass RESETB=0V VCC=0V
4 - 15
Chapter 4. EPROM
Lock bit write mode (1/3)
12Clock
8Clock
OSC1
1
2
2
VCC RESETB
6V 0V 12.5V 0000 0000
K3 ~ K0
EPROM Mode Lock Write ( 0100 )
K Port Latch
Lock bit write mode (2/3)
OSC1
3
VCC 6V
4
RESETB K3 ~ K0
12.5V 1110 1100
Write cycle Repeat 10 times
Repeat 2 times
Lock bit Write
4 - 16
Chapter 4. EPROM
Lock bit write mode (3/3)
START
c Reset (Set Lock bit write mode)
e
Wait cycle
Count=0
e
Write cycle *1
*1 Repeat until near 100uS. When 4MHz OSC1, repeat 10 times (12uS * 10 = 120uS)
e Delay cycle (Repeat 2 times)
Count++
No Count=10 Yes RESETB=0V VCC=0V
END
4 - 17
Chapter 4. EPROM
Lock bit read mode (1/2)
12Clock
8Clock
OSC1
1
2
3
You can strobe at any time from here
VCC RESETB K3 ~ K0 D5
6V 0V Lock Read Mode ( 0101 ) 12.5V 1101 Lock bit output 1101
K Port Latch
Lock bit read mode (2/2)
START c Reset (Set Lock bit read mode) e
Wait cycle
e
Read Lock bit (D5)
RESETB=0V VCC=0V
END
4 - 18

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